1. Technical Field
This disclosure relates to semiconductor devices and methods for fabrication thereof and more particularly, to body-contacts formed in a vertical transistor memory cell to avoid floating body problems.
2. Description of the Related Art
Semiconductor memory devices, which include vertical transistors often rely on outdiffusion from buried straps to form a connection between a deep trench storage node and a contact. As shown in FIG. 1, a top view of a partially fabricated dynamic random access memory chip 10 is shown. Four memory cells are depicted, each memory cell includes a deep trench 14. Active areas 16 include diffusion regions. Adjacent to active areas 16 are formed isolation trenches 18 filled with a dielectric material. A buried strap 20 is shown for one of the memory cells 12. A collar 22 of an adjacent cell and two adjacent isolation trenches 18 form a three-sided isolation region encapsulating buried strap 20.
Referring to FIG. 2, a cross-sectional view, taken at section line 2xe2x80x942 of FIG. 1, is shown. Memory cell 12 includes a vertical transistor 26 employed for accessing a storage node 28 in deep trench 14. When scaling down sizes of memory cells, buried strap 20 outdiffusion regions begin to extend as far as a neighboring memory cell""s collar regions 23. Buried strap 20 may form an extended outdiffusion region 30, which may extend to the collar 23 of a neighboring memory cell 21. If contact is made with the neighboring cell""s collar 22 by region 30, pinch-off of the access transistor 26 begins to occur. For memory cells which feature vertical access transistors surrounded by a 3-sided isolation, as shown in FIG. 1, floating body effects may arise, similar to those encountered in silicon on insulator structures, if the buried strap""s outdiffusion 30 reaches the opposite isolating collar 22 and pinches off the contact to the transistor body.
Floating body effects are caused when the body of a transistor gets electrically isolated from a conductive medium by either an insulator or an area with opposite doping (junction). In silicon on insulator (SOI) transistor structures, an insulator separates two silicon structures, one of which includes a channel region of the transistor device (e.g., transistor body). The potential at the transistor channel cannot be set to a specific value, but changes according to the voltage conditions applied to the adjacent source/drain junctions (i.e., the transistor channel voltage is floating and adjusts thermodynamically to its surroundings). Hence, the transistor threshold voltage changes with varying body bias, leading to parasitic leakage from the transistor. This is undesirable.
Similar effects, as described above with reference to FIGS. 1 and 2, are encountered in vertical transistor structures if the transistor body is disconnected from the silicon substrate by a lower source, drain junction.
Therefore, a need exists for a structure and method for forming said structure, which eliminates floating body potentials in memory devices with vertical transistors.
A semiconductor memory cell, in accordance with the present invention includes a deep trench formed in a substrate. The deep trench includes a storage node in a lower portion of the deep trench, and a gate conductor formed in an upper portion of the deep trench. The gate conductor is electrically isolated from the storage node. An active area is formed adjacent to the deep trench and is formed in the substrate to provide a channel region of an access transistor of the memory cell. A buried strap is formed to electrically connect the storage node to the active area when the gate conductor is activated. A body contact is formed opposite the deep trench in the active area and corresponding in position to the buried strap to prevent floating body effects due to outdiffusion of the buried strap. Methods for forming the body contact are also described.
In alternate embodiments, the body contact is preferably integrally formed from the substrate. The body contact may include a portion of a p-well of the substrate. The body contact may include portions that extend into isolation trenches, the isolation trenches being formed adjacent to the active area. The memory cell may be formed on a semiconductor memory chip having a plurality of memory cells, the memory chip including body contacts formed thereon which extend across a plurality of memory cells through isolation trenches, the isolation trenches being formed adjacent to active areas of the memory cells.
A method for forming a body contact for semiconductor memory devices with vertical access transistors, in accordance with the present invention, includes forming a stepped portion in an isolation trench of a first deep trench capacitor memory cell wherein the stepped portion is in contact with a dielectric sidewall of a trench capacitor cell of a memory cell located adjacent to the first memory cell. The dielectric sidewall is disposed opposite to a buried strap region of the first memory cell and disposed vertically between a source region and a drain region of a vertical access transistor of the first memory cell. The stepped portion is connected to a p-well formed in a substrate of the memory device to form a body contact to prevent floating body effects in the vertical access transistor.
In other methods, the step of forming may include the steps of providing a spacer mask to mask the stepped portion, and etching the substrate to form the stepped portion. The step of providing a spacer mask may include the steps of depositing a mask layer over portions of the substrate, patterning the mask layer, and patterning the substrate in accordance with the mask layer to form the stepped portion. The first memory cell may include a collar dielectric formed in a trench of the first deep trench capacitor and the step of providing a spacer mask may further include the steps of selectively etching the substrate relative to the collar dielectric and in accordance with an active area isolation trench mask to recess the substrate back from the collar dielectric to form collar portions which extend above the etched substrate, conformally depositing a mask layer over the collar portions and the substrate, patterning the mask layer, and patterning the substrate in accordance with the mask layer to form the stepped portion. The step of conformally depositing a mask layer may include the step of conformally depositing a silicon layer over the collar portions and the substrate. The step of patterning the mask layer may include the steps of doping first portions of the silicon layer by performing an angled implantation in which dopants are blocked from second portions of the silicon layer and selectively etching away the second portions to pattern the mask layer. The step of selectively etching away the second portions may include performing a wet ammonium hydroxide etch. The stepped portion may extend into the isolation region.
Another method for forming a memory cell including body contacts for preventing floating body effects for memory cell access transistors, in accordance with the present invention includes the steps of forming storage nodes and dielectric collars in deep trenches, the deep trenches being formed in a substrate, patterning isolation trenches into the substrate by selectively etching the substrate relative to the collar dielectric to provide collar dielectric portions which extend above a surface of the etched substrate, depositing a layer of silicon over the collar dielectric and the substrate, doping the silicon layer in selected portions by performing angled dopant implantation such that non-selected portions of the silicon are shielded from dopants by the collar dielectric portions, removing the non-selected portions of the silicon layer and etching the substrate to deepen the isolation trenches in accordance with the selected portions of the silicon layer to form a stepped portion within isolation trenches, the stepped portion forming a body contact such that the body contact is disposed opposite to a buried strap junction formed by dopant outdiffusion from the storage node.
In other methods, the dopants may include boron. The step of removing the non-selected portions of the silicon layer may include performing a wet ammonium hydroxide etch to remove the non-selected portions. The stepped portion may be integrally formed from a p-well of the substrate. The memory cell access transistors may include vertical transistors, and the method may further include the step of forming a gate conductor in the deep trenches above the storage node to form a vertical transistor adjacent to the deep trench.
These and other objects, features and advantages of the present invention will become apparent from the following detailed description of illustrative embodiments thereof, which is to be read in connection with the accompanying drawings.